The present invention relates to a semiconductor device and semiconductor fabrication techniques. More particularly, the present invention relates to a semiconductor device in which a plurality of semiconductor elements and/or regions are electrically isolated from each other by grooves formed in a semiconductor substrate, and to a technique of isolating elements which can be effectively utilized for the formation of element-isolating regions in a semiconductor integrated circuit device.
Elements in semiconductor integrated circuit devices are isolated by a pn junction isolation method using diffusion layers or by an oxidation film isolation method utilizing local oxidation films formed over the surface of the substrate. With these isolation methods, however, the widths of the isolation regions are relatively wide. As the size of the elements becomes smaller, therefore, the isolation regions occupy proportionally larger areas. This makes it difficult to obtain LSI (large-scale integrated) circuits in a very densely integrated form. The applicants have therefore proposed an isolation technique called the U-groove isolation method in which portions that act as isolation regions between active regions of elements are cut to form U-shaped grooves (moats or trenches, hereinafter referred to as U-grooves). A silicon dioxide film is formed within the U-grooves which are then filled with polycrystalline silicon. These form element-isolating regions.
This technique has been disclosed in, for example, the journal "NIKKEI ELECTRONICS", March 29, 1982, No. 287, pp. 90-101.
Such isolation method of isolating semiconductor devices by forming grooves in a semiconductor substrate and filling the grooves with insulative material requires a smaller space and attains a smaller parasitic capacitance than a pn junction isolation method and it is suitable to a high integration and high speed LSI. However, in this method, if the grooves on the surface after the insulating material has been filled in the grooves are wide, it is difficult to flatten the surface and a very complex process is required to flatten the surface. Accordingly, the width of the grooves is restricted to facilitate the flattening. However, when the width of the isolation grooves is restricted, parasitic active regions are created in the devices on the opposite sides of the groove and wiring capacitance increases. This results in a reduction of operation speed of the circuit.
The fact that a propagation delay time of 0.3 ns/gate with an isolation capacitance of 0.2 pF is attained by forming grooves in a semiconductor integrated circuit substrate is disclosed in an article Japanese Journal of Applied Physics, Volume 21 (1982) Supplemental 21-1, pages 37-40.
U.S. Pat. No. 4,396,460, directed to subject matter invented by the authors of the above article and filed on May 21, 1982, discloses a method for flattening an area of a wide isolation groove.
Bipolar transistors are the main elements in the construction of a bipolar type of semiconductor integrated circuit device. However, bipolar transistors must be isolated from each other by U-grooves when they are very densely arranged on a semiconductor substrate.
To reduce the size of a bipolar transistor, however, an n.sup.+ -type semiconductor region that acts as a collector contact region must be isolated by an insulating material from a p.sup.+ -type base region.